1. Field
This disclosure relates generally to circuits, and more specifically, to a circuit and method for reducing potential damage to an integrated circuit during an electrostatic discharge event.
2. Related Art
This disclosure relates generally to circuits, and more specifically, to a circuit and method for reducing potential damage to an integrated circuit during an electrostatic discharge event. An integrated circuit can be damaged when subjected to an overvoltage transient that is higher than the design voltage of the integrated circuit. Electrostatic discharge (“ESD”), originating from such sources as a mechanical chip carrier, a plastic chip storage device, or even a human being can generate a voltage that is many times greater than the design voltage of the integrated circuit. For example, the typical human body can supply an electrostatic discharge of 4 kilovolts or more. For integrated circuits that operate at voltages of less than, for example, 5V (volts), an electrostatic discharge of such proportions can be devastating. In order to protect the internal circuitry on integrated circuits from high voltage, or ESD events, protection circuits are utilized, generally between the internal circuitry and the input/output (“I/O”) terminals (e.g. pads, pins, bumps, etc.) of the integrated circuit.